Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes a module in terms of the behavior of a system describing signals that are generated and propagated through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
An HDL design can be synthesized to create a logical network list (netlist), which can be implemented within a particular programmable logic device. Prior to implementation, the HDL design can be simulated to determine whether the design will function as required. Wasted manufacturing costs due to faulty design may thereby be avoided. Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMS) and hardware description language (HDL) simulators.
One popular HDL language to use for development is VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language). In a VHDL simulator, VHDL procedures containing wait statements pose a modeling challenge. Similar to a VHDL process statement, a procedure may get suspended at a wait statement contained in the procedure. However, unlike a process statement, a procedure cannot be statically elaborated. This poses various complexities in the implementation of VHDL procedures.
A VHDL simulator generally includes a VHDL language compiler and a simulation kernel. The compiler converts input VHDL files into code that is executable by a simulation kernel. In generating the executable code, the compiler maps VHDL constructs into the language constructs of a target language. The target language may be a general programming language such as C/assembly, or some other proprietary language. Every process statement in a VHDL design is compiled into a function in the target language. In addition, every VHDL procedure is also compiled into a unique function in the target language. When simulation begins, the simulation kernel reads in the executable code generated by the compiler and executes the code according to the VHDL language rules. In particular, a simulation kernel generally executes VHDL functions corresponding to processes in a loop. Like an operating system kernel, functions corresponding to active processes are scheduled according to a scheduling algorithm, such as round robin, and executed by the kernel for a specific period of time. After a function has been executed the kernel executes the other functions. When all processes have been executed, the kernel executes the functions again as scheduled. In this manner functions corresponding to processes are simulated in a loop.
When the compiled function for a process, say p0, encounters a wait statement, the simulation kernel, executes functions corresponding to other processes while waiting for p0's wait to mature. Enabling a return to the simulation kernel during a wait is performed by recording the code location to which the process needs to resume after the wait statement has expired. The VHDL objects, upon which the process operates, are statically elaborated and persist in a global memory space throughout the simulation run. Simple C labels can be used to model resumption points in p0. When a wait statement is encountered a label is created at the location of the next statement to be executed after the wait. When the compiled function corresponding to p0 is called, the function will resume at the statement following the wait by jumping to the label using a goto statement.
If the process calls a VHDL procedure which does not have a wait statement, the compiled function of the procedure in the target language is simply invoked from within the compiled function of the process. Resumption points do not need to be recorded or used. Example 1 below shows a VHDL code sample of a process and two procedures that do not contain wait statements.                procedure foo2 (variable aa: integer; variable bb: out integer) is variable vv: integer:=aa*2;                    begin                            bb:=vv;                                    end procedure;            procedure foo1 (variable aa1, aa2: in integer; variable bb: out integer) is                            variable vv1: integer;                variable vv2: integer;                                    begin                            vv1:=aa1+aa2;                foo2(vv1, vv2);                bb:=vv2/vv1;                                    end procedure;                        p0: process                    variable v1, v2, v3: integer;                        begin                    v1:=10;            v2:=20;            wait for 5 ns;            foo1 (v1, v2, v3);            wait;                        end process        